It is a modern trend to fabricate electronic devices in ever light weight and in ever small thicknesses and sizes yet realizing high degrees of functions, integration and high signal processing speeds. Accompanying this trend, the semiconductor devices, too, are changing their forms. Namely, the semiconductor devices used to be of such a form that the lead terminals which are electrically conducting wirings were drawn out like a gull wing from the side surfaces of the package such as QFP (quad flat package). But, now, the semiconductor devices are of such a form that the electrodes are formed by using gold bumps or the like on the lower surface of the package such as BGA (ball grid array) making it possible to strikingly decrease the areas occupied by the semiconductor devices which are mounted on a mother board.
As a semiconductor device which is smaller than the BGA, a CSP (chip size package) is now drawing attention mounting a semiconductor chip which is an electronic part on a rigid substrate that is an insulating substrate made of, for example, ceramics relying upon such a method as flip-chip-mounting.
According to the above-mentioned conventional semiconductor device, an area occupied by each semiconductor device can be decreased on the mother board by decreasing the size of the package. However, since it is a modern trend to add new functions to the electronic devices, the number of the semiconductor devices mounted on the mother board is on the increase arousing a problem that the size of the mother board must be increased to meet the demand.
In such semiconductor devices, further, not only the mother board becomes large but also the lead terminals become very long from a principal semiconductor device to other semiconductor devices accompanied by a delay in the signals, distortion of signals and an increase in the consumption of electric power, making it difficult to accomplish the desired electric performance. In media equipment in which the circuit system operates at high speeds and possesses a large capacity, in particular, a decrease in the length of the lead terminals casts an important meaning.
Despite the mother board is realized in a small size, only one semiconductor device is permitted to be mounted on a mounting region for mounting a semiconductor device on the mother board. Therefore, this rather imposes limitation on the number of the semiconductor devices that can be mounted on the mother board.
Methods of solving the above problem have heretofore been proposed in, for example, Japanese Patent Publication (Laid-open) No. 223683/1998, Japanese Utility Model Publication (Laid-open) No. 61150/1988 and Japanese Patent Publication (Laid-open) No. 106509/1995, according to which wirings, solder balls, inner leads, via holes and through holes are provided on the insulating films or on the insulating sheets on which a semiconductor chip is mounted, and the insulating films or the insulating sheets are successively laminated one upon another, and are electrically connected together through the wirings, solder balls, inner leads, via holes and through holes.
With this method, however, it is difficult to confirm by eyes the connection among the insulating films and the insulating sheets. Besides, the insulating films or the insulating sheets that are laminated must be partly or entirely sealed with a resin. Therefore, even in case the device becomes partly defective, it is not easy to repair the defective part, still leaving room for improvement.
There has further been proposed a laminated multi-chip semiconductor device as disclosed in Japanese Patent No. 3033315 according to which insulating substrates of a polyimide or the like on which an electronic part such as an IC is bonded by inner leads, are laminated, and the outer leads of the upper layer and the outer leads of the lower layer are successively and electrically connected together by the outer leads which are electrically conducting wirings extending along the peripheral edges of the thus laminated insulating substrates.
In this case, however, the insulating substrate must have a predetermined size to maintain strength at the junction portion between the inner leads of the insulating substrate and the electrodes of the electronic part. In laminating the insulating substrate, further, a spacer of a predetermined thickness must be provided on the portion of the outer leads to avoid the contact between the electronic part of the upper layer and the inner leads of the lower layer, still leaving room for improvement from the standpoint of realizing the semiconductor devices in small sizes and in decreased thicknesses.
It is therefore a first object of the present invention to provide a semiconductor device preventing the electrically conducting wirings from being folded at the time of connecting the electrically conducting wirings to the electrodes of the electronic part on each insulating substrate, decreasing the size of the insulating substrate to a required minimum limit, and decreasing the size of the package as small as possible from the standpoint of practical use.
As disclosed in Japanese Patent Publication (Laid-open) No. 14979/1995, there has also been proposed a device in which leadless chip carriers mounting semiconductor memories are successively laminated in a mounting case via an insulating sheet, and the thus laminated chip carriers are electrically connected together in a manner that the end-surface through-hole electrodes formed in the side surfaces come in contact with the signal lines in the mounting case.
This, however, is not still enough for confirming by eyes the connection among the laminated chip carriers. Besides, to connect the chip carriers together, it becomes necessary to separately provide the mounting case and the internal signal lines, resulting in an increase in the number of parts and complex constitution still leaving room for improvement.
It is therefore a second object of the present invention to provide a semiconductor device which enables the laminated insulating substrates to be easily and reliably connected together electrically as a result of easily inspecting, by eyes, the connection among the laminated semiconductor devices, and simplifying the constitution by decreasing the number of parts of the semiconductor device.
A third object is to prevent the electrically conducting wirings from being folded at the time of connecting the ends of the electrically conducting wirings to the electrodes of the electronic part.
A fourth object is to stably laminate plural insulating substrates on which the electronic part is mounted.
A fifth object is to prevent the laminated insulating substrates from collapsing previously before the electric conduction is accomplished.
A sixth object is to prevent the plural electrically conducting wirings from collapsing.
A seventh object is to easily position the plural insulating substrates in laminating these insulating substrates on which the electronic parts are mounted.
A eighth object is to withstand the concentration of stress generated among the electrically conducting wirings at the corners of the insulating substrates due to internal strain caused by heat at the time of accomplishing the electric connection.
An ninth object is to form an alignment mark for positioning without increasing the number of parts.
A tenth object is to easily form the alignment mark for positioning.